IC74163 Integrated Presettable Synchronous 4-bit Modulo-16 Up counter. The IC is a synchronous counter as all 4 flip-flops are integrated into the same chip & they receive the same clock pulse (clock signal). The IC74163 is a completely programmable binary counter due to its four preset inputs, which allow it to begin counting with any loaded input by sending a low signal to the load pin. For cascading counters with n-bit synchronous counting, a ripple-carry (RC) output terminal is provided. IC 74163, 74193 74161, etc. are 4-bit binary counters. & IC 7490, 74160, 74190, etc. are the decade counter chips. Find most basic details about the counter circuit on Decade counter IC7490.
Features of IC74163:
- Typical clock frequency 32MHz
- Typical Power dissipation 93mW
- 4-Bit Modulo-16 Up counter.
- Preset inputs are available
- Synchronously programmable
- Internal look-ahead (Ripple carry) for fast counting
- Carry output for n-bit cascading
- Active low load control line to load input number
- Active low Reset terminal to reset the chip at any point.
- Typical propagation time, clock to Q output 14ns
Block Diagram of IC74163-:
The self-explanatory block diagram of IC74163 is shown in the figure below. If you understand this block diagram, you will be able to design any type of mod-n counter using this IC.
|Clock input||Clock signal input|
|ENP||Enable Parallel(Active High)|
|ENT||Enable Trickle(Active High)|
|Load||Synchronous Parallel Load/Load(Active Low) Input|
|Reset/Clear||Synchronous Active low clear to reset the IC|
|Ripple Carry||Ripple carry is used in cascading|
|A,B,C, & D||Preset Inputs(Parallel Data Inputs)|
What is meant by Synchronous Clear?
Synchronous clear means it is in sync with a clock signal, which means with the next clock signal, the outputs advance to the next count. You need to supply 8 rising clock pulses to reset the IC at a count of 7. You will understand the whole concept once I design mod 7 counter with 74163.
Functional Description of Pins-:
- It is also known as clock pulse/clock signal, its continuous high-low signal which will use to trigger IC, that’s why it is also known as triggering pulse.
- All 4 flip-flops are triggered with the same clock signal in this IC or any synchronous counter.
- ENP and ENT are the two enable inputs of the IC74163. Both ENP (Enable Parallel) and ENT (Enable Trickle) should be set to a high value in order to increase the count.
- Both enable pin is active high
- If the clock signal is supplied to ic and If the enable terminals received a low signal, the IC will not enable and will not begin counting. for more details refer mode selection table.
Load(Active Low input)-:
- Load this is active low input(logic 0) used to load the data to flip-flop output, If this terminal is supplied with the logic high then the loaded preset input will not be shown in the output.
- If any count is loaded to preset input pins & Low signal(logic 0) is applied to the load terminal then the IC will start counting with the loaded input
- If any count is loaded to preset input pins & high signal(logic 1) is applied to the load terminal, the counting starts with 0000.
Clear (Active Low Input)-:
- This is also known as Master Reset Input, and its used to reset the whole IC.
- If this terminal receives an active low signal then it will wait for the next clock signal to reset the output. that’s why it’s known as synchronous clear input.
- Mode Selection Table:
Clear Load ENT ENP Action on the rising clock edge 0 X X X All 4 flip-flop outputs cleared 1 0 X X Load preset inputs data(A, B, C, & D) to Qn 1 1 1 1 Increment Count 1 1 0 X No change (Hold) 1 1 X 0 No change (Hold)
Ripple Carry (R/C logic 0 to 1)-:
- The Ripple Carry terminal (Carry look-ahead circuitry) goes from logic 0 to logic 1, once the IC reaches its maximum count i.e. 1111(15), this signal is used in cascading of IC74163.
- The output of R/C (Ripple Carry) is directly connected to the enable pins of the second IC. As a result, the 2nd IC is only triggered once after each 15th count.
- The 2nd IC gets enabled only once after every 15 counts since the ripple carry goes only once logic 0 to logic 1 after every 15 counts.
Preset Inputs (A, B, C, & D)-:
- A B, C, & D are the present input, in which A is the Least Significant Bit (LSB) and D is the Most Significant Bit (MSB).
Flip-Flop Output (Qn)-:
- Qa, Qb, Qc, & Qd are the outputs terminals in which Qa is the Least Significant Bit(LSB) and Qd is the Most Significant Bit(MSB).
Pin Diagram of IC74163-:
The next figure has a self-explanatory pin diagram of IC74163; if you read the figure properly, you will not require to do any more research or briefing on the pinouts.
|Pin Number||Description||Pin Number||Description|
|1||Active Low Clear Input||9||Active low Load Input|
|2||Clock Signal Input||10||Active High ENT Input|
|3||A(LSB)||Preset Inputs to Load Data||11||Qd(MSB)||Flip-Flop Outputs|
|7||Active High Input ENP||15||RCO(Ripple Carry Output logic 0 to 1)|